rfLPC
A low level library for using NXP's LPC17xx SoC. Config is given for MBED prototyping board
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Macros | |
#define | RFLPC_SPI_CPOL_RISING_EDGE 0 |
Configure SCL to generate a rising edge clock. More... | |
#define | RFLPC_SPI_CPOL_FALLING_EDGE 2 |
Configure SCL to generate a falling edge clock. More... | |
#define | RFLPC_SPI_CPHA_PHASE_PIOR_TO_FIRST_EDGE 0 |
Transmit data before first clock edge. More... | |
#define | RFLPC_SPI_CPHA_PHASE_FIRST_EDGE 1 |
Transmit data at first clock edge. More... | |
Enumerations | |
enum | rflpc_spi_t { RFLPC_SPI0, RFLPC_SPI1 } |
Used to select which SPI port to use. More... | |
enum | rflpc_spi_mode_t { RFLPC_SPI_MASTER, RFLPC_SPI_SLAVE } |
Used to select the SPI operating mode. More... | |
Functions | |
void | rflpc_spi_init (rflpc_spi_t port, rflpc_spi_mode_t mode, rflpc_clock_divider_t cpu_clock_divider, uint8_t data_size_transfert, uint8_t clock_prescale, uint8_t serial_clock_rate, uint8_t clock_polarity_phase) |
Inits the SPI interface in master mode. More... | |
static LPC_SSP_TypeDef * | rflpc_spi_get_base_addr (rflpc_spi_t port) |
Returns the base address of the SPI control block depending of the desired port. More... | |
static int | rflpc_spi_tx_fifo_empty (rflpc_spi_t port) |
Tests if transmition FIFO is empty. More... | |
static int | rflpc_spi_idle (rflpc_spi_t port) |
Test if the spi is idle (nor transmiting neither receiving) This is useful when you need to handle CS by hand. More... | |
static int | rflpc_spi_tx_fifo_full (rflpc_spi_t port) |
Tests if the transmition FIFO is full. More... | |
static int | rflpc_spi_rx_fifo_empty (rflpc_spi_t port) |
Tests if the reception FIFO is empty. More... | |
static void | rflpc_spi_write (rflpc_spi_t port, uint16_t data) |
Sends data through the spi interface. More... | |
static uint16_t | rflpc_spi_read (rflpc_spi_t port) |
Receive data through the spi interface. More... | |
void | rflpc_spi_set_rx_callback (rflpc_spi_t port, rflpc_irq_handler_t callback) |
Sets the interrupt handler for SPI reception. More... | |
#define RFLPC_SPI_CPHA_PHASE_FIRST_EDGE 1 |
#define RFLPC_SPI_CPHA_PHASE_PIOR_TO_FIRST_EDGE 0 |
Transmit data before first clock edge.
#define RFLPC_SPI_CPOL_FALLING_EDGE 2 |
Configure SCL to generate a falling edge clock.
#define RFLPC_SPI_CPOL_RISING_EDGE 0 |
Configure SCL to generate a rising edge clock.
enum rflpc_spi_mode_t |
enum rflpc_spi_t |
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inlinestatic |
Returns the base address of the SPI control block depending of the desired port.
port | the port to get |
Definition at line 86 of file spi.h.
References RFLPC_SPI0.
Referenced by rflpc_spi_idle(), rflpc_spi_read(), rflpc_spi_rx_fifo_empty(), rflpc_spi_tx_fifo_empty(), rflpc_spi_tx_fifo_full(), and rflpc_spi_write().
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inlinestatic |
Test if the spi is idle (nor transmiting neither receiving) This is useful when you need to handle CS by hand.
port | The SPI port to test |
Definition at line 109 of file spi.h.
References rflpc_spi_get_base_addr().
void rflpc_spi_init | ( | rflpc_spi_t | port, |
rflpc_spi_mode_t | mode, | ||
rflpc_clock_divider_t | cpu_clock_divider, | ||
uint8_t | data_size_transfert, | ||
uint8_t | clock_prescale, | ||
uint8_t | serial_clock_rate, | ||
uint8_t | clock_polarity_phase | ||
) |
Inits the SPI interface in master mode.
port | The port to configure |
mode | The mode to use |
cpu_clock_divider | The divider applied to CPU clock to get the SPI peripheral clock |
data_size_transfert | the number of bits that are transfered in each frame (only values between 4 and 16bits are supported) |
clock_prescale | Factor by which the prescaler divide the peripheral clock. Between 2 and 254. Bit 0 is always read as 0 (only even numbers). Used only for master mode |
serial_clock_rate | Number of prescaler-outputs ber bit. This allows to set the SPI tranfert clock. Used only for master mode. |
clock_polarity_phase | Clock polarity and phase. polarity is bit 1, phase is bit 0. Other bits are ignored. Can be constructed as a ORed combination of RFLPC_SPI_CPOL_* and RFLPC_SPI_CPHA_* values |
In slave mode, the clock_prescale and serial_clock_rate parameters are not used. The clock sent by the master must not exceed 1/12 of the frequency used to clock the SPI peripheral
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inlinestatic |
Receive data through the spi interface.
port | the port to receive from |
Definition at line 159 of file spi.h.
References rflpc_spi_get_base_addr(), and rflpc_spi_rx_fifo_empty().
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inlinestatic |
Tests if the reception FIFO is empty.
port | The SPI port to test |
Definition at line 134 of file spi.h.
References rflpc_spi_get_base_addr().
Referenced by rflpc_spi_read().
void rflpc_spi_set_rx_callback | ( | rflpc_spi_t | port, |
rflpc_irq_handler_t | callback | ||
) |
Sets the interrupt handler for SPI reception.
The interrupt will be generated when the RX FIFO is half-full
port | the port to use |
callback | the callback to set |
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inlinestatic |
Tests if transmition FIFO is empty.
port | The SPI port to test |
Definition at line 97 of file spi.h.
References rflpc_spi_get_base_addr().
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inlinestatic |
Tests if the transmition FIFO is full.
port | The SPI port to test |
Definition at line 122 of file spi.h.
References rflpc_spi_get_base_addr().
Referenced by rflpc_spi_write().
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inlinestatic |
Sends data through the spi interface.
port | The port to send to |
data | The data to send. If the port has been configured to send less than 16 bits in each frame, the data must be right justified |
Definition at line 147 of file spi.h.
References rflpc_spi_get_base_addr(), and rflpc_spi_tx_fifo_full().