spi.h

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/* This file is part of rflpc. Copyright 2010-2011 Michael Hauspie
 *
 * rflpc is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * rflpc is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with rflpc.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __RFLPC_SPI_H__
#define __RFLPC_SPI_H__
/*
  Author: Michael Hauspie <michael.hauspie@univ-lille1.fr>
  Created:
  Time-stamp: <2014-05-29 15:05:59 (mickey)>
*/

#ifdef RFLPC_CONFIG_ENABLE_SPI

#include "../clock.h"
#include "../interrupt.h"

typedef enum
{
   RFLPC_SPI0, 
   RFLPC_SPI1  
} rflpc_spi_t;

typedef enum
{
    RFLPC_SPI_MASTER, 
    RFLPC_SPI_SLAVE,  
} rflpc_spi_mode_t;

#define RFLPC_SPI_CPOL_RISING_EDGE 0

#define RFLPC_SPI_CPOL_FALLING_EDGE 2

#define RFLPC_SPI_CPHA_PHASE_PIOR_TO_FIRST_EDGE 0

#define RFLPC_SPI_CPHA_PHASE_FIRST_EDGE 1


extern void rflpc_spi_init(rflpc_spi_t port, rflpc_spi_mode_t mode, rflpc_clock_divider_t cpu_clock_divider, uint8_t data_size_transfert, uint8_t clock_prescale, uint8_t serial_clock_rate, uint8_t clock_polarity_phase);

static inline LPC_SSP_TypeDef *rflpc_spi_get_base_addr(rflpc_spi_t port)
{
    return (port == RFLPC_SPI0) ? LPC_SSP0 : LPC_SSP1;
}

static inline int rflpc_spi_tx_fifo_empty(rflpc_spi_t port)
{
   LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);
   return spi_base->SR & 1;
}

static inline int rflpc_spi_idle(rflpc_spi_t port)
{
   LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);
   return ((spi_base->SR & 0x10) == 0);
}


static inline int rflpc_spi_tx_fifo_full(rflpc_spi_t port)
{
   LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);
   return !(spi_base->SR & (1UL << 1));
}

static inline int rflpc_spi_rx_fifo_empty(rflpc_spi_t port)
{
   LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);
   return !(spi_base->SR & (1UL << 2));
}

static inline void rflpc_spi_write(rflpc_spi_t port, uint16_t data)
{
   LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);   
   while (rflpc_spi_tx_fifo_full(port));
   spi_base->DR = data;
}

static inline uint16_t rflpc_spi_read(rflpc_spi_t port)
{
    LPC_SSP_TypeDef *spi_base = rflpc_spi_get_base_addr(port);    
    while (rflpc_spi_rx_fifo_empty(port));
    return spi_base->DR;
}

extern void rflpc_spi_set_rx_callback(rflpc_spi_t port, rflpc_irq_handler_t callback);


#endif /* ENABLE_SPI */


#endif